1. Field of the Invention
The present invention relates to a semiconductor device configured to reduce an electric field concentration in the vicinity of its isolation region and thereby to increase its withstand voltage characteristic.
2. Background Art
As one of conventional power semiconductor devices, a lateral double diffused metal oxide semiconductor field effect transistor (hereinafter, referred to as an LDMOSFET) has been known. The LDMOSFET is, for example, integrated on the same semiconductor chip as other signal processing circuits are integrated, and used as a driver circuit. There, in one region over a top surface of an isolation region thereof, a drain electrode for applying a high electric potential to a drain region of the LDMOSFET is drawn to the outside in a manner straddling the isolation region. In the isolation region located under the drain electrode, a diffusion region less doped than the isolation region is extended from the isolation region toward the drain region. There has been known a technology which, with this structure, reduces the electric field concentration in the vicinity of an edge of the isolation region straddled by the drain electrode to increase a withstand voltage between a drain and a source. This technology is described for instance in Japanese Patent Application publication No. Hei10(1998)-242452 (pp. 6 to 8 and FIGS. 1 to 3).
The conventional LDMOSFET for high voltage use is integrated on the same chip as other signal processing circuits (for example, a control circuit and a logical circuit) are integrated, and forms a high voltage  integrated circuit. A structure thereof is such that, in an epitaxial layer laminated on a semiconductor substrate, there is formed an isolation region stretching from a surface of the epitaxial layer and reaching the substrate. A region where the LDMOSFET is formed is electrically insulated and isolated from other element formation regions by an isolation region. In one region above a top surface of the isolation region, a drain electrode for applying a high electric potential to a drain region of the LDMOSFET is drawn to the outside in a manner straddling the isolation region. In the isolation region located under the drain electrode, a conductive layer which is electrically connected to the isolation region is formed so that the conductive layer covers a top surface of a junction region between the epitaxial layer and the isolation region. There has been known a technology which, by having this structure, reduces the electric field concentration in the vicinity of an edge of the isolation region straddled by the drain electrode to increase the withstand voltage between a drain and a source. This technology is described for instance in Japanese Patent Application publication No. Hei9(1997)-260503 (pp. 4 to 6 and FIGS. 1 to 5).
As described above, in the conventional LDMOSFET, in order to reduce the electric field concentration in the vicinity of an edge of an isolation region straddled by a drain electrode, the diffusion region less doped than the isolation region is extended from the isolation region toward the drain region. Furthermore, the drain region is formed in a region away from the isolation region by forming the diffusion region, which has the electric potential equal to that of the isolation region, in a manner extending toward the drain region. With this structure, under the above diffusion region, an invalid region where the LDMOSFET is not arranged is formed. Therefore, there is the problem that element formation regions are not efficiently arranged with respect to a chip size.
Additionally, in the conventional LDMOSFET, in order to reduce the electric field concentration in the vicinity of the edge of the isolation region  located under the drain electrode, the conductive layer extending from a top surface of the isolation region toward the drain region is formed. There, the conductive layer has the electric potential equal to that of the isolation region. With this structure, the conductive layer is allowed to have a shielding effect against the drain electrode. On the other hand, the conductive layer has a field plate effect which influences an electric potential distribution formed in an epitaxial layer. Specifically, in the drain region, it is required to reduce an influence from the conductive layer by providing a larger separation distance between the conductive layer and the epitaxial layer. This structure involves a necessity of thickening an insulating film on a top surface of the epitaxial layer, and there is a problem that a higher manufacturing cost is required.
Additionally, in the conventional LDMOSFET, in order to reduce the electric field concentration in the vicinity of the edge of the isolation region located under the drain electrode, the conductive layer extending from the top surface of the isolation region toward the drain region is formed. The conductive layer is formed stepwise so that a separation distance from the epitaxial layer comes to be larger in a region closer to the drain region. There, the conductive layer is formed of metal such as aluminum or a low-resistant material such as polysilicon. With this structure, fine patterning in a small region between the conductive layer and the drain region is required, and there is a problem that complication of manufacturing processes is brought about. Furthermore, since film thicknesses of an insulating film under the conductive layer are varied, a dedicated process for forming the conductive layer is required. Thereby, there is a problem that a higher manufacturing cost is required.